做世界一流芯片

Nan Sun is Professor with Tsinghua University since 2020. He was Assistant and then tenured Associate Professor with University of Texas at Austin. He received B.S. degree from Tsinghua University in 2006, and Ph.D. degree from Harvard University in 2010. Dr. Sun received the NSF Career Award in 2013, and the IEEE SSCS New Frontier Award in 2020. He has published 28 JSSC papers and 47 ISSCC/VLSI/CICC papers. He has graduated 22 PhD students, 8 of whom are professors at top universities in the US and China. He serves on the Technical Program Committee of CICC and ASSCC. He was Associate Editor of TCAS-I, and a Guest Editor of JSSC. He serves as Distinguished Lecturer for IEEE Circuits-and-Systems Society from 2018 to 2020.

Interests

  • IC design
  • analog
  • mixed-signal
  • data converters

Education

  • Ph.D. degree, 2010

    School of Engineering and Applied Sciences, Harvard University, Cambridge, MA, USA

  • B.S. degree (Hons.), 2006

    the Department of Electronic Engineering, Tsinghua University, Beijing, China

Team members

Director

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Nan Sun

Professor

IC design, analog, mixed-signal, data converters

Co-advisor

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Jie Lu

Assistant Professor in SIC

ADC/DAC, Reconfigurable Mixed-Signal IC, Mixed-Signal Computing

Postdoc

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Yanquan Luo

Postdoctoral Researcher

Analog and mixed signal IC design, ADC, DAC, Sensor analog front-end design

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Yi Zhong

Postdoctoral Researcher

Oversampling data converter design, Low-power scaling-friendly oversampling data converter design

Student

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Chaoyang Xing

Ph.D. Student

Mixed Signal

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Mingtao Zhan

Ph.D. Student

Mixed Signal, In-Memory Computing

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Mingyang Gu

Ph.D. Student

High speed analog-to-digital converters, Digitally assisted analog-to-digital converters

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Xing Wang

Ph.D. Student

Mixed-signal IC design

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Yunsong Tao

Ph.D Student

High-speed analog-to-digital converter, Mixed-signal circuit

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Zhishuai Zhang

Ph.D. Student

Mixed Signal

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Zijie Gao

Ph.D. Student

Mix-signal IC design

Team@UT Austin

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Wei Shi

Ph.D. Student

Mixed signal IC

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Xiangxing Yang

Ph.D. Student

Mixed Signal, In-Memory Computing

PhD Students Graduated

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Abhishek Mukherjee

Cirrus Logic

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Arindam Sanyal

Assistant Professor at SUNY Buffalo

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Chen-Kai Hsu

ADI IC Engineer

Mixed-signal ICs, High-performance Data Converters

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Kareem Ragab

Broadcom

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Linxiao Shen

Assistant professor in Peking University

Mixed Signal, Analog Circuits and Systems

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Long Chen

Engineer in Google

Mixed Signal Circuits Design

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Shaolan Li

Assistant Professor in Gatech

Analog Mixed-Signal Integrated Circuit Design, Hardware Accelerator for Deep Learning, Ultrasound-On-Chip, Electronic Design Automation

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Wenda Zhao

Analog and mixed-signal IC design engineer in Apple Inc.

Analog and Mixed-signal IC

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Wenjuan Guo

Analog/Mixed-Signal Design Engineer in Apple Inc.

Mixed Signal

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Xiyuan Tang

Assistant professor in Peking University

Mix-signal IC

Jointly Supervised PhD Students Graduated

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Denquan Li

Associate Professor in Xidian University

Mixed Signal IC Design, High-speed ADC

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Haoyu Zhuang

Assistant Professor in University of Electronic Science and Technology of China

Mixed-signal Integrated Circuits, Pipelined ADC, SAR ADC, Bandgap Reference, Physically Unclonable Function

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Jiaxin Liu

Professor in UESTC

Mixed Signal Integrated Circuits, ADC

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Xin Xin

Assistant Professor at Xi’an Youdian University

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Yanlong Zhang

Associate Professor at Xi’an Jiaotong University

RF,Analog, and Mixed-signal IC Design, High-Performance Frequency Sources, Data Converters

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Yi Shen

Associate Professor in Hangzhou Dianzi University

Mixed Signal, ADC

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Yi Zhong

Postdoctoral Researcher

Oversampling data converter design, Low-power scaling-friendly oversampling data converter design

Master Students Graduated

Visiting Scholars

Publications

An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier

OJSSCS, 2021
An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier

10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR

ISSCC, 2021
10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR

15.2 A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating

ISSCC, 2021
15.2 A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating

A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping

JSSC, 2021 (CICC invited submission)
A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier

JSSC, 2020 (ISSCC invited submission)
A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier

A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS

JSSC, 2021
A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS

A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration

JSSC, 2020
A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration

An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter

JSSC, 2020
An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter

16.5 A 13b 0.005mm2 40MS/s SAR ADC with kT/C Noise Cancellation

ISSCC, 2020
16.5 A 13b 0.005mm2 40MS/s SAR ADC with kT/C Noise Cancellation

9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier

ISSCC, 2020
9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier

Recruitment

Contact

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