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An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier

JSSC, 2020 (VLSI invited submission)

A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣ M Structure

JSSC, 2020 (CICC invited submission)

A Fractional- N PLL With Space–Time Averaging for Quantization Noise Reduction

JSSC, 2020 (CICC invited submission)

A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS

JSSC, 2020

A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique

JSSC, 2020 (CICC invited submission)

An OTA-Less Second-Order VCO-Based CT ΔΣ Modulator Using an Inherent Passive Integrator and Capacitive Feedback

JSSC, 2020

A Two-Step ADC With a Continuous-Time SAR-Based First Stage

JSSC, 2019

A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Tri-Level Voting

JSSC, 2019

A 0.029-mm2 17-fJ/Conversion-Step Third-Order CT ΔΣ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer

JSSC, 2019

A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure

JSSC, 2018