A 10-b 800-MS/s Time-Interleaved SAR ADC With Fast Variance-Based Timing-Skew Calibration


This paper presents a time-interleaved (TI) SAR analog-to-digital converter (ADC) with a fast variance-based timing-skew calibration technique. It uses a single-comparator-based window detector (WD) to calibrate the timing skew. The WD can suppress variance estimation errors and allow precise variance estimation from a significantly small number of samples. It has low-hardware cost and orders of magnitude faster convergence speed compared to prior variance-based timing-skew calibration technique. The proposed technique brings collateral benefit of offset mismatch calibration. After timing-skew calibration, a prototype 10-b 800-MS/s ADC in 40-nm CMOS achieves the Nyquist-rate SNDR of 48 dB and consumes 4.9 mW, leading to the Walden FoM of 29.8-fJ/conversion step.

IEEE Journal of Solid-State Circuits ( Volume: 52, Issue: 10, Oct. 2017)