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Analog-to-digital converter (ADC)
A Fully Dynamic Low-Power Wideband Time-Interleaved Noise-Shaping SAR ADC
JSSC, 2021
A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping
JSSC, 2021 (CICC invited submission)
A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier
JSSC, 2020 (ISSCC invited submission)
A 13-bit 0.005-mm2 40-MS/s SAR ADC With kT/C Noise Cancellation
JSSC, 2020 (ISSCC invited submission)
A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS
JSSC, 2021
A Pipeline SAR ADC With Second-Order Interstage Gain Error Shaping
JSSC, 2020 (VLSI invited submission)
A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣ M Structure
JSSC, 2020 (CICC invited submission)
A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS
JSSC, 2020
A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique
JSSC, 2020 (CICC invited submission)
An OTA-Less Second-Order VCO-Based CT ΔΣ Modulator Using an Inherent Passive Integrator and Capacitive Feedback
JSSC, 2020
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