phase-locked loop (PLL)

A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣ M Structure

JSSC, 2020 (CICC invited submission)

A Fractional- N PLL With Space–Time Averaging for Quantization Noise Reduction

JSSC, 2020 (CICC invited submission)