Jiaxin Liu | 清华大学孙楠教授实验室主页

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An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier
A Fully Dynamic Low-Power Wideband Time-Interleaved Noise-Shaping SAR ADC
10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR
15.2 A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating
27.1 A 250kHz-BW 93dB-SNDR 4th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering
27.4 A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier
A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping
A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier
A 13-bit 0.005-mm2 40-MS/s SAR ADC With kT/C Noise Cancellation
A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration
An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter
16.5 A 13b 0.005mm2 40MS/s SAR ADC with kT/C Noise Cancellation
9.3 A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2nd-Order Mismatch Error Shaping
9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier
A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Tri-Level Voting
18.2 A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter
A 0.029-mm2 17-fJ/Conversion-Step Third-Order CT ΔΣ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer