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Shaolan Li

An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier
A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier
An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter
A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣ M Structure
A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS
An OTA-Less Second-Order VCO-Based CT ΔΣ Modulator Using an Inherent Passive Integrator and Capacitive Feedback
A Two-Step ADC With a Continuous-Time SAR-Based First Stage
18.2 A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter
3.4 A 0.01mm2 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor
A 0.029-mm2 17-fJ/Conversion-Step Third-Order CT ΔΣ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer
A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure
A 13-ENOB 2nd-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure
A 174.3-dB FoM VCO-Based CT ΔΣ Modulator With a Fully-Digital Phase Extended Quantizer and Tri-Level Resistor DAC in 130-nm CMOS

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