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An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier

OJSSCS, 2021

A 51-pJ/Pixel 33.7-dB PSNR 4× Compressive CMOS Image Sensor With Column-Parallel Single-Shot Compressive Sensing

JSSC, 2021

A Fully Dynamic Low-Power Wideband Time-Interleaved Noise-Shaping SAR ADC

JSSC, 2021

A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping

JSSC, 2021 (CICC invited submission)

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier

JSSC, 2020 (ISSCC invited submission)

A 13-bit 0.005-mm2 40-MS/s SAR ADC With kT/C Noise Cancellation

JSSC, 2020 (ISSCC invited submission)

A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS

JSSC, 2021

A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration

JSSC, 2020

An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter

JSSC, 2020

A Pipeline SAR ADC With Second-Order Interstage Gain Error Shaping

JSSC, 2020 (VLSI invited submission)