A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping


This article presents an enhanced interstage gain error shaping (GES) technique that adopts a digital error feedback (DEF) method to address the truncation error in the prior implementation, which can extend the interstage gain error tolerance by five times. The proposed DEF technique does not introduce additional errors as it operates purely in the digital domain. This article also proposes a first-order passive quantization noise shaping (NS) technique that reduces the input-pair ratio of the two-input-pair comparator by 2.7 times, thus alleviating the noise penalty caused by using a multiple-input-pair comparator. A prototype analog-to-digital converter (ADC) equipped with the proposed techniques in a 40-nm CMOS technology achieves a 77.1-dB signal-to-noise-and-distortion ratio (SNDR) over 6.25-MHz bandwidth while operating at 100 MS/s and consuming 1.38 mW. It achieves a 173.7-dB Schreier figure of merit (FoM).

IEEE Journal of Solid-State Circuits ( Volume: 56, Issue: 3, March 2021)