successive approximation register (SAR)

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier

JSSC, 2020 (ISSCC invited submission)

A 13-bit 0.005-mm2 40-MS/s SAR ADC With kT/C Noise Cancellation

JSSC, 2020 (ISSCC invited submission)

A Two-Step ADC With a Continuous-Time SAR-Based First Stage

JSSC, 2019

A 0.029-mm2 17-fJ/Conversion-Step Third-Order CT ΔΣ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer

JSSC, 2019

A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure

JSSC, 2018

A 6-bit 0.81-mW 700-MS/s SAR ADC With Sparkle-Code Correction, Resolution Enhancement, and Background Window Width Calibration

JSSC, 2018

An Energy-Efficient Hybrid SAR-VCO ΔΣ Capacitance-to-Digital Converter in 40-nm CMOS

JSSC, 2017

A 0.7-V 0.6-μW 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction

JSSC, 2017